Eeprom with erasing gate adjacent floating gate and control gate

ABSTRACT

A structure of a floating gate type EEPROM capable of implementing micromachining less than submicron and a method for fabricating it are disclosed. Since a silicon oxide film  3  for element isolation is embedded in an P-type Si substrate  1 , as compared with the case where the element isolation region is formed on the P-type Si substrate  1 , a level difference between the P-type Si substrate  1  and a floating gate electrode  6 , control gate electrode  8  and erasing gate electrode  12  can be reduced remarkably. This solves a problem of etching remainder during the dry etching of each electrode. In addition, the depth of focus in lithography can be easily assured. This realizes a floating gate type EEPROM equipped with an erasing gate which is so fine as to be less than submicron.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] The present application is a division of application Ser. No.09/099,615 filed on Jun. 18, 1998.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory deviceand more particularly, to a floating gate type EEPROM (ElectricallyErasable and Programmable Read Only Memory) equipped with an erasinggate electrode and a method for fabricating the same.

[0004] 2. Description of the Related Art

[0005] In recent years, a floating gate type EEPROM, as a non-volatilesemi conductor memory device capable of holding written information withno power supply, has been used for an internal and external memorydevice for a variety of computers.

[0006] Now, several kinds of structures of the floating gate type EEPROMare proposed. One of them is a structure in which an erasing gateelectrode is provided in the vicinity of a floating gate (for example,see JP-A-4-340767). FIGS. 13A and 13B to FIGS. 18A and 18B and 18c aresequential step sectional views, in each of which figure A shows asection taken in line B-B′ of figure B, and figure B shows a sectiontaken in line A-A′ in figure A. Incidentally, FIG. 18C is a view showingan peripheral region adjacent to the structure shown in FIG. 18B. InFIG. 18C, reference numeral 32S denotes an electric wiring pattern of aperipheral circuit formed in the same step as the erasing gate electrode32.

[0007] First, as seen from FIGS. 13A and 13B, the one main surface of aP-type silicon (Si) 21 is selectively subjected to ion implantation toform N-type diffusion layers 22 a and 22 b. These N-type diffusionlayers serve as a source and a drain of a memory cell, respectively.

[0008] As seen from FIGS. 14A and 14B, by a known CVD technique, asilicon oxide film 23 for element isolation is formed on the P-type Sisubstrate 21. By selective dry etching using a photoresist, a prescribedarea of the silicon oxide film 23 is removed selectively. Subsequently,by the known CVD technique, another silicon oxide film is formed on theentire surface. Thereafter, by anisotropic dry etching, a side wall film24 made of silicon oxide is formed on the side wall of the silicon oxidefilm 23.

[0009] As seen from FIGS. 15A and 15B, by a thermal oxidation technique,a silicon oxide film 25 serving as a gate oxide film is formed on theexposed area of the P-type Si substrate 21. Thereafter, by the known CVDtechnique, a polycrystalline silicon (poly-Si) film 26 is formed on theentire surface. Using the selective dry etching using photoresist, witha prescribed area of the poly-Si film 26 left, the remaining area isremoved. This poly-Si film 26 serves as a floating gate electrode.

[0010] As seen from FIGS. 16A and 16B, by the thermal oxidationtechnique, a silicon oxide film 27 is formed on the entire surface. Bythe known CVD technique, a poly-Si film 28 is formed thereon.Thereafter, by the known CVD technique, a silicon oxide film 29 isformed, and further, using the selective dry etching using photoresistas a mask, with a prescribed area of the silicon-oxide film 29 left, theremaining area is removed. Subsequently, using as a mask the siliconoxide film 29, a prescribed area of the poly-Si film 28 and the siliconoxide film 27 is selectively removed subsequently. The poly-Si film 28serves as a control gate electrode.

[0011] As seen from FIGS. 17A and 17B, by the known CVD technique, asilicon oxide film 30 is formed on the entire surface. Subsequently, bythe anisotropic dry etching, a side wall film made of the silicon oxidefilm 30 is formed on the side wall of the silicon oxide film 29 andpoly-silicon film 28. Thereafter, using as a mask the silicon oxidefilms 29 and 30, with a prescribed area of the underlying poly-Si film26 being left, its remaining unnecessary portion is removed.

[0012] As seen from FIGS. 18A-18c, by the thermal oxidation technique, asilicon oxide film 31 serving as a tunnel film is formed on the exposedarea of the side of the poly-Si film 26. Subsequently, by the known CVDtechnique, a poly-Si film 32 is formed. Further, by the selective dryetching technique using photoresist, with a prescribed pattern of thepoly-Si film 32 being left, its remaining area is removed to form anerasing gate electrode made of the poly-Si film 32.

[0013] Further, metallic wirings (not shown) will be made for the N-typediffusion layers 22 a and 22 b serving as a source and a drain, thepoly-Si film 28 serving as a control gate electrode and poly-Si film 32serving as an erasing gate electrode.

[0014] An explanation will be given of the operation of thesemiconductor memory device thus fabricated.

[0015] In a write operation, a voltage of 12 V is applied to the poly-Sifilm 28 serving as a control gate electrode, and the P-type Si substrate21 and the N-type diffusion layer 22 a serving as a source region aregrounded. Simultaneously, a voltage pulse signal having a height of 10 Vand width of 10×10⁻⁶ sec is applied to the N-type diffusion layer 22 bserving as a drain region. Then, hot electrons are generated in thevicinity of the boundary between the N-type diffusion layer 22 b and theP-type Si substrate 21. Part of them is pulled by the potential of thepoly-Si film 26 which has been enhanced due to coupling so that they areinjected into the poly-Si film 26 through the silicon oxide film 25.They remain stored in the poly-Si film 26 serving as a floating gateeven after completion of application of the voltage pulses. Thus, thewrite operation is completed.

[0016] In an erase operation, with the poly-Si film 28 serving as thecontrol gate electrode, P-type Si substrate 21, N-type diffusion layer22 a serving as the source region and N-type diffusion layer 22 b beinggrounded, voltage pulses having a height of 15 V and width of 1×10⁻³ secare applied to the poly-Si film 32 serving as the erasing gateelectrode. During the application of the voltage pulses, the electronswhich have been stored in the poly-Si film 26 serving as the floatinggate electrode move to the poly-Si film 32 through the silicon oxidefilm 31. The electrons in the poly-Si film 26 are eventually dischargedto complete the erasing operation.

[0017] In a read operation, with the P-type substrate 21 and N-typediffusion layer 22 a serving as the source region being grounded,voltages of 5 V and 1.5 V are applied to the poly-Si film 28 serving asthe control gate electrode and the N-type diffusion layer 22 b servingas the drain region, respectively. In this state, a current flowingbetween the N-type diffusion layer serving as the drain region and theN-type diffusion layer 22 a serving as the source region is read.

[0018] In the floating gate type EEPROM subjected to the writeoperation, when it serves as a MOS (Metal-Oxide-Silicon) transistor, thethreshold voltage is boosted owing to the electrons stored in thefloating gate electrode of the poly-Si film 26 so that the currentflowing between the N-type diffusion layer 22 b serving as the drainregion and the N-type diffusion layer 22 a serving as the source regionbecomes several pA or less. On the other hand, in the floating gate typeEEPROM subjected to the erase operation, the threshold voltage islowered as compared with when it is in the written state so that acurrent of several μA— several tens of μA flows by the above readoperation.

[0019] Thus, in terms of the current flowing the N-type diffusion layer22 b serving as the drain region and the N-type diffusion layer 22 aserving as the source region, the written state and erased state of thefloating gate EEPROM can be discriminated from each other.

[0020] However, the conventional floating gate type EEPROM having anerasing gate electrode has the following defects. In such an EEPROM, onan element isolation film which is a CVD film formed on the surface ofan Si substrate, the floating gate electrode, control gate electrode anderasing electrode are successively stacked. Therefore, when the floatinggate electrode, control electrode and erasing gate electrode and erasinggate electrode are formed, a very large level difference occurs betweeneach electrode and the surface of the Si substrate. Particularly,assurance of the depth of focus in lithography of the erasing gateelectrode may become difficult, or etching remainder is apt to occurduring the dry etching. This makes it difficult to effect micromachiningless than submicron.

SUMMARY OF THE INVENTION

[0021] An object of the present invention is to solve the above problemin the prior art to provide a floating gate type semiconductor memorydevice having an erasing gate electrode which provides a small leveldifference between a floating gate electrode, control gate electrode anderasing gate electrode and the surface of an Si substrate, and can beeasily micromachined.

[0022] Another object of the present invention is to provide a methodfor fabricating such a floating gate type semiconductor memory device.

[0023] In order to attain the above objects, in accordance with thefirst aspect of the present invention there is provided a semiconductordevice comprising: an element isolation region formed in a semiconductorsubstrate having a first conductivity type; a source region and a drainregion formed in an element forming region surrounded by the elementisolation region, the source region and drain region having a secondconductivity type opposite to the first conductivity type; a firstinsulating film formed on the element forming region; a floating gateelectrode formed on the first insulating film; a second insulating filmformed on the floating gate electrode; a control gate electrode formedon the second insulating film; a third insulating film formed on thefloating gate electrode; and an erasing gate electrode formed so as toface to the floating gate electrode through the third insulating film tobe a tunneling medium.

[0024] In accordance with the same aspect of the present, there isprovided a method for fabricating a semiconductor memory devicecomprising the steps of: in a semiconductor substrate having a firstconductivity type, forming a source region and a drain region having asecond conductivity opposite to the first conductivity type; forming atrench having a prescribed thickness from a main surface of thesemiconductor substrate toward inside thereof in an area to be anelement isolation region of the semiconductor substrate; embedding anelement isolation insulating film in the trench; forming a firstinsulating film on an element forming region of the semiconductorsubstrate isolated by the element isolation insulating film; forming afloating gate electrode on the first insulating film; forming a secondinsulating film on the floating gate electrode; forming a control gateelectrode on the second insulating film; forming a third insulating filmto be a tunneling medium on a side of the floating gate electrode; andforming an erasing gate electrode so as to cover the third insulatingfilm.

[0025] In accordance with the second aspect of the present invention,there is provided a semiconductor memory device comprising: aninsulating film for element isolation formed at a prescribed portion ona semiconductor substrate having a first conductivity type; asemiconductor layer embedded in a portion not covered by the insulatingfilm on the semiconductor substrate; a source region and a drain regionformed in the semiconductor layer and having a second conductivity typeopposite to the first conductivity type; a first insulating film formedat a prescribed area of the semiconductor layer; a floating gateelectrode formed on the first insulating film; a second insulating filmformed on the floating gate electrode; a control gate electrode formedon the second insulating film ; a third insulating film formed on thefloating gate electrode ;and an erasing gate electrode formed on thethird insulating film so as to face to the floating gate electrode.

[0026] In accordance with the same aspect of the present invention,there is a method for fabricating a semiconductor device comprising thesteps of: forming a first insulating film on a semiconductor substratehaving a first conductivity type; making an opening portion to be anelement forming region of the first insulating film; forming asemiconductor layer having a first conductivity type in the openingportion; forming a source region and a drain region in the semiconductorlayer, the source region and drain region having a second conductivitytype opposite to the first conductivity type; forming a secondinsulating film at a prescribed portion of the semiconductor substrate;forming a floating gate electrode on the second insulating film; forminga third insulating film on a prescribed portion of said floating gateelectrode; forming a control electrode on the third insulating film;forming a fourth insulating film to be a tunneling medium on a side ofthe floating gate electrode; and forming an erasing gate electrode so asto cover the fourth insulating film.

[0027] In accordance with the present invention, in the floating gatetype EEPROM equipped with an erasing gate electrode, by embedding theinsulating film inside the Si substrate to implement element isolation,a level difference between the Si substrate and the floating gateelectrode, control gate electrode, erasing gate electrode can be reducedremarkably. The etching remainder is difficult to occur during the dryetching of each electrode, particularly during etching of the erasinggate electrode. In addition, the depth of focus in lithography can beeasily assured when the erasing gate electrode is formed. This makes itvery easy to effect micromachining less than submicron as compared withthe prior art and fabricating method, and greatly contributes to realizethe high integration of the floating gate type semiconductor memorydevice.

[0028] Additionally, since the erasing gate electrode and the wiringpattern in a peripheral circuit are generally formed in the same step, alarge level difference occurs therebetween, thus making it impossible toeffect the lithography at high precision. On the other hand, inaccordance with the present invention, since the element isolationregion of the memory area is constructed of the trench formed in thesemiconductor substrate, or the element region is arranged in a regionsurrounded by the element isolation film in the surface of thesemiconductor substrate, the erasing gate electrode has a structurelowered by the thickness of element isolation region as compared withthe prior art structure. Therefore, the level difference is decreased sothat the lithography can be effected at high precision. Thus, anon-volatile memory can be fabricated with high precision and highreliability.

[0029] The above and other objects and features of the present inventionwill be more apparent from the following description of the presentinvention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIGS. 1A and 1B to FIGS. 8A , 8B and 8C are sequential stepsectional views of a semiconductor memory device for explaining thefirst embodiment of the present invention.

[0031]FIGS. 9A and 9B are sectional views of a semiconductor memorydevice for explaining the modified first embodiment of the presentinvention.

[0032]FIGS. 10A and 10B to FIGS. 12A and 12B are sequential stepsectional views of a semiconductor memory device for explaining thesecond embodiment of the present invention.

[0033]FIGS. 13A and 13B to FIGS. 18A, 18B and 18C are sequential stepsectional views for explaining one example of a conventional method forfabricating a semiconductor memory device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Embodiment 1

[0035]FIGS. 1A and 1B to FIGS. 8A, 8B and 8C are sequential stepsectional views for explaining the method for fabricating asemiconductor memory device according to the present invention. In eachof the figures, FIG. A shows a section taken in line B-B′ of FIG. B, andFIG. B shows a section taken in line A-A′ in FIG. A. Incidentally, FIG.8C is a view showing an peripheral region adjacent to the structureshown in FIG. 8B. Reference symbol 12S denotes an electric wiringpattern of a peripheral circuit formed in the same step as an erasinggate electrode 12.

[0036] First, as shown in FIGS. 1A and 1B, using photoresist as a mask,As⁺ions are selectively implanted under the condition of 40 keV and1×1¹⁵cm⁻² to form N-type diffusion layers 2 a and 2 b. The N-typediffusion layers 2 a and 2 b serve as a source and drain of a memorycell, respectively.

[0037] As seen from FIGS. 2A and 2B, an opened portion serving anelement isolation region of the P-type Si substrate 1 is made by theselective anisotropic dry etching using a photoresist. In thisembodiment, by dry etching under a condition of power of 200 W andpressure of 20 Pa using HBr gas, a trench, which has a depth of about300 nm from the surface of the P type Si substrate 1 and a width of 0.35μm, is formed. Now, in order to realize good embedding, the width of thetrench is preferably not larger than 0.35 μ and the depth thereof ispreferably not larger than 400 nm. Incidentally, in this case, an N-typediffusion layer serving as a punch-through stopper may be formed on thebottom of the trench.

[0038] As seen from FIGS. 3A and 3B, on the entire surface of the P-typeSi substrate 1, a silicon oxide film 3 having a thickness of about 600nm is formed by a known CVD technique so that it is embedded in theopened element isolation region. A photoresist 13 is applied on theentire surface to flatten the resultant surface.

[0039] As seen from FIGS. 4A and 4B, by an etch-back technique with thephotoresist and silicon oxide film controlled at substantially the sameetching rate, etching is done so that the Si substrate 1 is exposed.Thus, the silicon oxide film 3 is embedded in only the opened portion ofthe P-type Si substrate 1 so as to constitute an element isolation film.

[0040] As seen from FIGS. 5A and 5B, by a thermal oxidation technique,the surface of the P-type Si substrate 1 is oxidized to form a siliconoxide film 5 serving as a gate oxide film and having a thickness ofabout 30 nm. On the silicon oxide film 5, a phosphorus doped poly-Sifilm 6 having a thickness of 200 nm is formed under temperature of 620°C. or higher. Thereafter, by the selective dry etching technique using aphotoresist, with a prescribed portion thereof being left, the remainingportion thereof is etched away.

[0041] As seen from FIGS. 6A and 6B, by the thermal oxidation, a siliconoxide film 7 having a thickness of about 25 nm is formed on the exposedportion of the P-type Si substrate 1 and on the phosphorus-doped poly-Sifilm 6. On the silicon oxide film 7, a phosphorus-doped poly-Si film 8having a thickness of about 200 nm is formed.

[0042] Further, by a known CVD technique, on the phosphorus dopedpoly-Si film 8, a silicon oxide film 9 having a thickness of about 300nm is formed. By the selective dry etching technique using aphotoresist, the silicon oxide film 9 is partially etched away.Thereafter, using the silicon oxide film 9 as a mask, thephosphorus-doped poly-Si film 8 is partially etched in a self-alignedmanner. The phosphorus-doped poly-Si film 8 constitutes a control gateelectrode. The silicon oxide film 9 serves to electrically insulate thecontrol gate electrode and an erasing gate electrode formed later fromeach other.

[0043] As seen from FIGS. 7A and 7B, by the known CVD technique, asilicon oxide film 10 having a thickness of about 200 nm is formed. Bythe anisotropic dry etching, the silicon oxide film 10 is etched to forma side wall film having a thickness of about 150 nm, which is made ofthe silicon oxide film 10, on the side wall of the phosphorus-dopedpoly-Si film 8 and the silicon oxide film 9. Subsequently, using, as amask, the silicon oxide films 9 and 10, the underlying phosphorus-dopedpoly-Si film 6 is etched away in a self-aligned manner. At this time,the phosphorus-doped poly-Si film 6 is electrically disconnected fromthe outside to constitute a floating gate electrode.

[0044] As seen from FIGS. 8A and 8B, the exposed portion of the sidewall of the phosphorus-doped poly-Si film 6 is oxidized to form asilicon oxide film 11 having a thickness of about 40 nm. Thereafter, aphosphorus-doped poly-Si film 12 is formed on the entire resultantsurface. By the selective dry etching, the phosphorus-doped poly-Si film12 is partially etched away to form an erasing gate electrode. Thus, afloating gate type EEPROM memory cell equipped with an erasing gateelectrode is completed as shown in FIGS. 8A and 8B.

[0045] Incidentally, metallic wirings will be made for the N-typediffusion layers 2 a and 2 b serving as a source and drain;phosphorus-doped poly-Si film 8 serving as a control gate electrode; andphosphorus-doped poly-Si film 12 serving as an erasing gate electrode.This step will not be explained here.

[0046] In accordance with this embodiment, since the element isolationfilm is formed within the P-type Si substrate 1, as compared with theprior art in which the element isolation film is formed on the P-type Sisubstrate 1, the level difference between the P-type Si substrate 1 andthe floating gate electrode, control gate electrode, erasing gateelectrode can be reduced remarkably. The etching remainder is notsubstantially occurred during the dry etching of each electrode. Inaddition, the depth of focus in lithography can be easily assured. Thismakes it possible to effect micromachining less than submicron, ascompared with the prior art structure equipped with the elementisolation film of a CVD film on the Si substrate.

[0047] Additionally, as apparent from the comparison between FIG. 8C andFIG. 18C, in the prior art structure, a large level difference occursbetween the erasing gate electrode 32 and wiring pattern 32S which areformed in the same step, thus making it impossible to effect thelithography at high precision. On the other hand, in accordance with thepresent invention, as seen from FIG. 8C, since the element isolationregion of the memory area is constructed of the trench formed in thesemiconductor substrate, the erasing gate electrode has a structurelowered by the thickness of element isolation as compared with the priorart structure. Therefore, the level difference can be decreased so thatthe lithography can be effected at high precision. Thus, a non-volatilememory can be fabricated with high precision and high reliability.

[0048] In the above-described embodiment, as a technique for embeddingthe silicon oxide film 3 for element isolation, an etch-back techniqueusing a photoresist was used. However, it is needless to say that a CMP(chemical mechanical polishing) technique can be used to provide thesame effect.

[0049] Further, in the above-described embodiment, the silicon oxidefilm 3 for element isolation was embedded completely in the Si substrate1. However, it is needless to say that the structure in which thesilicon oxide film 3 is partially embedded as shown in FIGS. 9A and 9Bcan provide the same effect. Further, the element isolation film, whichwas a silicon oxide film in the above-described embodiment, may be anyother film as long as it permits electric insulation. For example, theisolation structure constituted by a trench formed in a siliconsubstrate, an oxide film formed by oxidation of the inner surface of thetrench, and poly-Si embedded within the trench can provide the sameeffect.

[0050] Embodiment 2

[0051] Referring to FIGS. 10A-12B, an explanation will be given of thesecond embodiment of the present invention.

[0052] As shown in FIGS. 10A and 10B, by the known CVD technique, ansilicon oxide film 3 for element isolation is formed on a Si substrate1. Subsequently, by the selective dry etching, with a prescribed portionthereof being left, the remaining portion is removed.

[0053] As shown in FIG. 11B, a epitaxial layer 14 having a thickness ofabout 300 nm is grown selectively on an region of the Si substrate 1exposed from the silicon oxide film 3.

[0054] Thereafter, like the first embodiment, in the epitaxial layer 14are formed a source 2 a, drain 2 b, and on the epitaxial layer 14 areformed silicon oxide film 5, phosphorus-doped poly-Si film 6 serving asa floating gate electrode, silicon oxide film 7, phosphorus-dopedpoly-Si film 8 serving as a control gate electrode, silicon oxide film9, silicon oxide film 10 serving as a side wall film, silicon oxide film11 serving as a tunneling oxide film and phosphorus doped poly-Si film12 serving as an erasing gate electrode. Thus, as shown in FIGS. 12A and12B, a floating gate type EEPROM equipped with an erasing gate electrodewill be completed.

[0055] This embodiment has an advantage of requiring a small number ofsteps for element isolation than in the first embodiment.

[0056] In both first and second embodiments, an explanation was given ofthe structure and fabricating method of the memory cell of thesplit-gate floating gate type EEPROM. However, it is needless to saythat the same effect can be obtained for the memory cell of a stack-gatefloating gate type EEPROM.

What is claimed is:
 1. A semiconductor device comprising: an elementisolation region embedded in a semiconductor substrate having a firstconductivity type; a source region and a drain region formed in anelement forming region surrounded by said element isolation region, saidsource region and drain region having a second conductivity typeopposite to said first conductivity type; a first insulating film formedon said element forming region; a floating gate electrode formed on saidfirst insulating film; a second insulating film formed on said floatinggate electrode; a control gate electrode formed on said secondinsulating film; a third insulating film formed on said floating gateelectrode; and an erasing gate electrode formed so as face said floatinggate electrode through said third insulating film to be a tunnelingmedium.
 2. The semiconductor memory device according to claim 1 ,wherein said third insulating film is formed on a side surface and apart of an upper surface of said floating gate electrode.
 3. Thesemiconductor memory device according to claim 1 , further comprising aperipheral circuit formed on a surface of said semiconductor substrate,wherein a wiring layer of said peripheral circuit and said erasing gateelectrode are made of a conductive layer formed by a same step.
 4. Asemiconductor memory device comprising: an insulating film for elementisolation formed at a prescribed portion on a semiconductor substratehaving a first conductivity type; a semiconductor layer embedded in aportion surrounded by said insulating film on said semiconductorsubstrate; a source region and a drain region formed in saidsemiconductor layer and having a second conductivity type opposite tosaid first conductivity type; a first insulating film formed at aprescribed area of said semiconductor layer; a floating gate electrodeformed on said first insulating film; a second insulating film formed onsaid floating gate electrode; a control gate electrode formed on saidsecond insulating film; a third insulating film formed on said floatinggate electrode; and an erasing gate electrode formed on said thirdinsulating film so as to face said floating gate electrode.
 5. Thesemiconductor memory device according to claim 4 , wherein said secondinsulating film is formed on a side and a portion of an upper surface ofsaid floating gate electrode.
 6. The semiconductor memory deviceaccording to claim 4 , further comprising a peripheral circuit formed ona surface of said semiconductor substrate, wherein a wiring layer ofsaid peripheral circuit and said erasing gate electrode are formed ofthe same conductive layer.